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ASAHI KASEI
[AK4380]
AK4380
100dB 24Bit 96kHz 2ch DAC
GENERAL DESCRIPTION The AK4380 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4380 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4380 integrates a combination of SCF and CTF filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. The 24 Bit word length and 96kHz sampling rate make this part ideal for a wide range of applications including DVD and AC-3 systems. The AK4380 is offered in a space saving 16pin TSSOP package. FEATURES o Sampling Rates Ranging from 8kHz to 96kHz o 128x Oversampling (Normal speed mode) o 64x Oversampling (Double speed mode) o 24Bit 8x FIR Digital Filter o 2nd order Analog LPF o On chip Buffer with Single End Output o Digital de-emphasis for 32k, 44.1k and 48kHz sampling o Soft mute o I/F format: 24bit MSB justified, 24/20/16bit LSB justified, I2S o Master clock: 256fs, 384fs, 512fs or 768fs (Normal speed mode) 128fs, 192fs, 256fs or 384fs (Double speed mode) o THD+N: -88dB o Dynamic Range: 100dB o High Tolerance to Clock Jitter o Power supply: 4.5 to 5.5V o Space Saving 16 Pin TSSOP (6.4mm x 5.0mm) Package
P/S MCLK VDD SMUTE/CSN DFS/CCLK DIF0/CDTI DZF
P Interface
De-emphasis Control
Clock Divider
VSS VCOM
LRCK BICK SDTI
Audio Data Interface
8X Interpolator 8X Interpolator
Modulator Modulator
LPF
AOUTL
LPF
AOUTR
PDN
VREF
MS0018-E-01 -1-
2000/8
ASAHI KASEI
[AK4380]
n Ordering Guide
AK4380VT AKD4380 -40 +85C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4380
n Pin Layout
MCLK BICK SDTI LRCK PDN SMUTE/CSN DFS/CCLK DIF0/CDTI 1 2 3 4 5 6 7 8 16 15 14 DZF VREF VDD VSS VCOM AOUTL AOUTR P/S
Top View
13 12 11 10 9
PIN/FUNCTION
Function Master Clock Input Pin An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin 5 PDN I Power-Down Mode Pin When at "L", the AK4380 is in the power-down mode and is held in reset. The AK4380 should always be reset upon power-up. 6 SMUTE I Soft Mute Pin in parallel mode "H": Enable, "L": Disable CSN I Chip Select Pin in serial mode 7 DFS I Double Speed Sampling Mode Pin in parallel mode "L": Normal Speed, "H": Double Speed CCLK I Control Data Input Pin in serial mode 8 DIF0 I Audio Data Interface Format Pin in parallel mode CDTI I Control Data Input Pin in serial mode 9 P/S I Parallel/Serial Select Pin (Internal pull-up pin) "L": Serial control mode, "H": Parallel control mode 10 AOUTR O Rch Analog Output Pin 11 AOUTL O Lch Analog Output Pin 12 VCOM O Common Voltage Pin, VDD/2 Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. 13 VSS Ground Pin 14 VDD Power Supply Pin 15 VREF I Voltage Reference Input Pin 16 DZF O Data Zero Input Detect Pin When SDTI of both channels follow a total 8192 LRCK cycles with "0" input data, this spin goes to "H". Note: All input pins except pull-up pin should not be left floating. No. 1 Pin Name MCLK I/O I
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ASAHI KASEI
[AK4380]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note: 1. All voltages with respect to ground. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 6.0 10 VDD+0.3 85 150 Units V mA V C C
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Power Supply Voltage Reference Symbol VDD VREF min 4.5 3.0 typ 5.0 max 5.5 VDD Units V V
(Note 2)
Note: 2. Analog output voltage scales with the voltage of VREF. AOUT (typ@0dB) = 3.4VppxVREF/5.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0018-E-01 -3-
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ASAHI KASEI
[AK4380]
ANALOG CHARACTERISTICS
(Ta = 25C; VDD = 5.0V; fs = 44.1kHz at DFS = "0"; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz 20kHz at fs = 44.1kHz, 20Hz 40kHz at fs = 96kHz; RL 10k; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 3) THD+N (0dB Output) fs = 44.1kHz -88 -82 dB fs = 96kHz -86 dB Dynamic Range (-60dB Output, A-weight) fs = 44.1kHz 92 100 dB fs = 96kHz 93 dB S/N (A-weight) fs = 44.1kHz 92 100 dB fs = 96kHz 93 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/C Output Voltage (Note 4) 3.15 3.40 3.65 Vpp Load Resistance 10 k Output Current 200 A Power Supplies Power Supply Current (VDD) Normal Operation (PDN = "H") 14 22 mA Power-Down Mode (PDN = "L") (Note 5) 10 100 A Power Supply Rejection (Note 6) 40 dB Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual. 4. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF, AOUT (typ@0dB) = 3.4VppxVREF/5. 5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS. 6. PSR is applied to VDD with 1kHz, 100mV. VREF pin is held +5V.
MS0018-E-01 -4-
2000/8
ASAHI KASEI
[AK4380]
FILTER CHARACTERISTICS
(Ta = 25C; VDD = 4.5 5.5V; fs = 44.1kHz; DEM0 = "1", DEM1 = "0") Parameter Symbol min Digital filter PB 0 Passband 0.05dB (Note 7) -6.0dB Stopband (Note 7) SB 24.25 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 8) GD Digital Filter + LPF FR Frequency Response 0 20.0kHz 40.0kHz typ max 20.0 0.02 19.1 0.2 0.3 Units kHz kHz kHz dB dB 1/fs dB dB
22.05
Notes: 7. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.4535xfs (@0.05dB), SB=0.546xfs. 8. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal.
DIGITAL CHARACTERISTICS
(Ta = 25C; VDD = 4.5 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout = -80A) Low-Level Output Voltage (Iout = 80A) Input Leakage Current (Note 9) Symbol VIH VIL VOH VOL Iin min 2.2 VDD-0.4 typ max 0.8 0.4 10 Units V V V V A
Note: 9. P/S pin has internal pull-up device, normally 100k.
MS0018-E-01 -5-
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ASAHI KASEI
[AK4380]
SWITCHING CHARACTERISTICS
(Ta = 25C; VDD = 4.5 5.5V; CL = 20pF) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode BICK Pulse Width Low Pulse Width High BICK "" to LRCK Edge (Note 10) LRCK Edge to BICK "" (Note 10) SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN "" to CCLK "" CCLK "" to CSN "" Reset Timing PDN Pulse Width (Note 11) Symbol fCLK dCLK fs Duty min 2.048 40 8 45 typ 11.2896 44.1 max 36.864 60 96 55 Units MHz % kHz %
tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tPD
1/128fs 1/64fs 70 70 40 40 40 40 200 80 80 40 40 150 50 50 150
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 10. BICK rising edge must not occur at the same time as LRCK edge. 11. The AK4380 can be reset by PDN= "L" upon power up. If MCLK frequency or DFS changes, the AK4380 should be reset by PDN pin or RSTN bit.
MS0018-E-01 -6-
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ASAHI KASEI
[AK4380]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL Serial Interface Timing
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ASAHI KASEI
[AK4380]
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0018-E-01 -8-
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ASAHI KASEI
[AK4380]
OPERATION OVERVIEW n System Clock
The external clocks, which are required to operate the AK4380, are MCLK, LRCK and BICK. The master clock (MCLK) corresponds to 256fs, 384fs, 512fs or 768fs (for normal speed mode; 128fs, 192fs, 256fs or 384fs for double speed mode). MCLK frequency is automatically detected, and the internal master clock becomes 256fs (for normal speed mode; 128fs for double speed mode). The MCLK should be synchronized with LRCK but the phase is not critical. Table 13 illustrate corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4380 is in the normal operation mode (PDN= "H"). If these clocks are not provided, the AK4380 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4380 should be reset by PDN= "L" after threse clocks are provided. If the external clocks are not present, the AK4380 should be in the power-down mode (PDN= "L"). After exiting reset at power-up etc., the AK4380 is in the power-down mode until MCLK and LRCK are input.
DFS pin / DFS bit LRCK Frequency (fs) MCLK Frequency
Normal Speed Mode "L" / "0" 8kHz~48kHz 256fs,384fs,512fs,768fs Table 1. System clock
Double Speed Mode "H" / "1" 8kHz~96kHz 128fs,192fs,256fs,384fs
LRCK fs 32.0kHz 44.1kHz 48.0kHz
256fs 8.1920MHz 11.2896MHz 12.2880MHz
MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
768fs 24.5760MHz 33.8688MHz 36.8640MHz
BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Table 2. System clock example (Normal Speed Mode)
LRCK fs 88.2kHz 96.0kHz
128fs 11.2896MHz 12.2880MHz
MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
384fs 33.8688MHz 36.8640MHz
BICK 64fs 5.6448MHz 6.1440MHz
Table 3. System clock example (Double Speed Mode)
MS0018-E-01 -9-
2000/8
ASAHI KASEI
[AK4380]
n Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 bits as shown in Table 4 can select five formats in serial mode. In parallel mode, the DIF0 pin as shown Table 5 can select two formats. In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 SDTI Format 16bit LSB Justified 20bit LSB Justified 24bit MSB Justified 24bit I2S Compatible 24bit LSB Justified BICK 32fs 40fs 48fs 48fs 48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2
Default
Table 4. Audio Data Formats (Serial mode)
Mode 2 3
DIF0 0 1
SDTI Format 24bit MSB Justified 24bit I2S Compatible
BICK 48fs 48fs
Figure Figure 3 Figure 4
Table 5. Audio Data Formats (Parallel mode)
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDTI Mode 0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
15
0
14
1
BICK (64fs) SDTI Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing
Rch Data
MS0018-E-01 - 10 -
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ASAHI KASEI
[AK4380]
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDTI Mode 1 SDTI Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1,4 Timing
Rch Data
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
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2000/8
ASAHI KASEI
[AK4380]
n De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is controlled by the DEM0 and DEM1 bits regardless of the status of DFS. DFS 0 0 0 0 1 1 1 1 DEM1 0 0 1 1 0 0 1 1 DEM0 0 1 0 1 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz 44.1kHz OFF 48kHz 32kHz Default
Table 6. De-emphasis filter control
MS0018-E-01 - 12 -
2000/8
ASAHI KASEI
[AK4380]
n Zero detection
When the input data at both channels is continuously zeros for 8192 LRCK cycles, DZF pin goes to "H". DZF pin channel immediately goes to "L" if the input data is not zero after going DZF "H". If RSTN bit is "0", DZF pin goes to "H". DZF pin goes to "L" at 4~5/fs after RSTN bit returns to "1".
n Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to "H", the output signal is attenuated by - during 1024 LRCK cycles. When the SMUTE pin is returned to "L", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE pin 1024/fs 0dB Attenuation (1) (3) 1024/fs
-
GD (2) AOUT (4) 8192/fs GD
DZF pin
Notes: (1) The output signal is attenuated by - during 1024 LRCK cycles (1024/fs). (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data at both channels is continuously zeros for 8192 LRCK cycles, DZF pin goes to "H". DZF pin immediately goes to "L" if the input data is not zero after going DZF "H". Figure 5. Soft mute and zero detection
MS0018-E-01 - 13 -
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ASAHI KASEI
[AK4380]
n System Reset
The AK4380 should be reset once by bringing PDN = "L" upon power-up. The AK4380 is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by MCLK. The AK4380 is in the power-down mode until MCLK and LRCK are input.
n Power-down
The AK4380 is placed in the power-down mode by bringing PDN pin "L" and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up.
PDN
Internal State D/A In (Digital)
GD
Normal Operation
Power-down
Normal Operation
"0" data
(1)
GD
D/A Out (Analog)
Clock In
MCLK, LRCK, BICK
(3) (4)
(2)
(3)
(1)
Don't care
DZF External MUTE
(6)
(5)
Mute ON
Notes: (1) The analog output corresponding to the digital input has a group delay, GD. (2) Analog outputs are floating (Hi-Z) at the power-down mode. (3) Click noise occures at the edges(" ") of PDN signal. This noise is output even if input data is "0". (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = "L"). (5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is shown in this figure. (6) DZF pin is "L" in the power-down mode (PDN = "L"). Figure 6. Power-down/up sequence example
MS0018-E-01 - 14 -
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ASAHI KASEI
[AK4380]
n Reset Function
When RSTN = "0", the AK4380's digital section is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pin goes to "H". Figure 7 shows the example of reset by RSTN bit. RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Digital Block Power-down
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
2/fs(5)
DZF Notes: (1) The analog output corresponding to the digital input has a group delay, GD. (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges(" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = "L"). (5) DZF pin goes to "H" when the RSTN bit becomes to "0", and goes to "L" at 2/fs after RSTN bit becomes to "1". (6) There is a delay, 3~4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2~3/fs from RSTN bit "1" to the internal RSTN "1". Figure 7. Reset sequence example
MS0018-E-01 - 15 -
2000/8
ASAHI KASEI
[AK4380]
n Mode Control Interface
Some function of AK4380 can be controlled by pins (parallel control mode) shown in Table 6. The serial control interface is enabled by the P/S pin = "L". Internal registers may be written by 3-wire P interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, CAD1/0; fixed to "01"), Read/Write (1bit; fixed to "1", Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4380 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN "". The clock speed of CCLK is 5MHz (max). The CSN and CCLK must be fixed to "H" when the register does not be accessed. Function Double speed De-emphasis SMUTE Zero Detection 16/20/24bit LSB justified format Parallel mode O X O O X Serial mode O O O O O
Table 7. Function list (O: available, X: not available) PDN = "L" resets the registers to their default values. When the state of P/S pin is changed, AK4380 should be reset by PDN= "L". In the serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized. CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data
Figure 8. Control I/F Timing * The AK4380 does not support the read command and chip address. C1, C0 and R/W are fixed to "011" * When the AK4380 is in the power down mode (PDN = "L") or the MCLK is not provided, writing into the control register is inhibited.
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ASAHI KASEI
[AK4380]
n Register Map
Addr 00H 01H Register Name Control 1 Control 2 D7 0 0 D6 0 0 D5 0 0 D4 DIF2 0 D3 DIF1 DFS D2 DIF0 DEM1 D1 PW DEM0 D0 RSTN SMUTE
Notes: For addresses from 02H to 1FH, data must not be written. When PDN pin goes "L", the registers are initialized to their default values. When RSTN bit goes "0", the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is "0".
n Register Definitions
Addr 00H Register Name Control 1 default D7 0 0 D6 0 0 D5 0 0 D4 DIF2 0 D3 DIF1 1 D2 DIF0 1 D1 PW 1 D0 RSTN 1
RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the AK4380 should be reset by PDN pin or RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (see Table 4) Initial: "011", Mode 3 Addr 01H Register Name Control 2 default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 DFS 0 D2 DEM1 0 D1 DEM0 1 D0 SMUTE 0
SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response Control (see Table 6) Initial: "01", OFF DFS: Sampling Speed Control (see Table 1) 0: Normal speed, 8kHz~48kHz 1: Double speed, 8kHz~96kHz
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ASAHI KASEI
[AK4380]
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4380) is available in order to allow an easy study on the layout of a surrounding circuit.
Analog 5V
Master Clock 64fs 24bit Audio Data fs Reset & Power down
1 2 3 4 5 6
MCLK BICK SDTI LRCK PDN SMUTE DFS DIF0
DZF VREF
16 15 14 0.1u 13 10u 12 11 10 9 + 10u + + 10u + 10u
Optional External Mute Circuits
AK4380
VDD VSS VCOM AOUTL AOUTR P/S
Lch Out
220 27k
Mode Setting
7 8
Rch Out
220 27k
System Ground
Analog Ground
Figure 9. Typical Connection Diagram (Parallel mode)
Analog 5V
Master Clock 64fs 24bit Audio Data fs Reset & Power down
1 2 3 4 5 6
MCLK BICK SDTI LRCK PDN CSN CCLK CDTI
DZF VREF
16 15 14 0.1u 13 10u 12 11 10 9 + 10u + + 10u + 10u
Optional External Mute Circuits
AK4380
VDD VSS VCOM AOUTL AOUTR P/S
Lch Out
220 27k
MicroController
7 8
Rch Out
220 27k
System Ground
Analog Ground
Figure 10. Typical Connection Diagram (Serial mode) Notes: - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and the load. - ALL input pins except internal pull-up pin should not be left floating. - Decoupling capacitor, especially 0.1F ceramic capacitor for high frequency should be placed as near to VDD and VREF pins as possible. - System ground including DSP/P should be separated from AK4380's VSS. Both grounds should be connected by one point at power supply or regulator on system board.
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ASAHI KASEI
[AK4380]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1F ceramic capacitor for high frequency should be placed as near to VDD as possible.
2. Voltage Reference
The differential Voltage between VREF and VSS pins set the analog output range. VCOM is a signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor attached to VREF and VCOM pins eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from VREF and VCOM pins in order to avoid unwanted coupling into the AK4380.
3. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range is typically 3.40Vpp (typ@VREF=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Therefore, any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
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ASAHI KASEI
[AK4380]
PACKAGE
16pin TSSOP (Unit: mm)
5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 0.10 010
Epoxy Cu Solder plate 2000/8 - 20 -
1 0.220.1
8 0.65
Seating Plane
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0018-E-01
4.4
ASAHI KASEI
[AK4380]
MARKING
AKM 4380VT XXYYY
1) 2)
3) 4)
Pin #1 indication Date Code : XXYYY (5 digits) XX: lot# YYY: Date Code Marketing Code : 4380VT Asahi Kasei Logo
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0018-E-01 - 21 -
2000/8

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Price & Availability of AKD4380

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